The present invention relates generally to switched capacitor circuits, and more particularly to offset-compensated switched-capacitor sample/hold circuits and to switched-capacitor ADCs (analog to digital converters), and more particularly to faster, lower cost circuitry for offset-compensated switched-capacitor sample/hold circuits and to switched-capacitor ADCs which include them.
In switched-capacitor ADCs utilized to sense a CMOS light sensor, it often is desirable to utilize the output of a switched-capacitor offset DAC to compensate for a “dark light offset voltage”, which is the output voltage produced by the CMOS sensor in the absence of any ambient light. That offset voltage must be subtracted from the CMOS sensor output voltage measured when the ambient light is present in order to obtain an accurate measurement of the ambient light intensity.
“Prior Art” FIGS. 1A and 1B show an offset-compensated switched-capacitor sample/hold circuit 1 which includes a basic switched capacitor sample/hold circuit 2 and a switched-capacitor offset DAC 3, the output of which is coupled to summing junctions at the inputs of a sample/hold amplifier 11. Switched-capacitor sample/hold circuit 2 includes a conventional switched-capacitor stage that samples input voltages Vin+ and Vin− onto input sampling capacitors 7A and 7B, respectively, each of which has a capacitance CIN. The sampled charge then is redistributed through conductors 9A and 9B onto feedback capacitors 12A and 12B, each of which has a capacitance CFB.
Switched-capacitor offset DAC 3 operates in response to a digital input signal B0,B1 . . . BM, where M=2N−1, typically to produce a “dark light” compensation signal on summing junction conductors 9A and 9B so that an analog output signal Vout+−Vout− produced by combined switched-capacitor sample/hold circuit 1 presents a value that accurately represents ambient light intensity of a CMOS light sensor which produces the input signal Vin+−Vin−. That value typically is applied to the input of an ADC. Switched-capacitor offset DAC 3 is a relatively large, costly circuit which includes 2N switched-capacitor stages 3−0,2 . . . 2N−1 as shown, or alternatively, switched-capacitor offset DAC 3 includes N binarily weighted switched-capacitor stages. (Note that using N binarily weighted switched-capacitor stages in switched-capacitor offset DAC 3 requires fewer capacitors, but the overall large amount of capacitance remains unchanged.)
Prior Art FIG. 2 shows a variation in which the switched-capacitor offset DAC is incorporated into the switched-capacitor input sampling stage 3A, as shown. In this case, the capacitors of the switched-capacitor offset DAC 3A also function as the sampling capacitors of the offset-compensated switched-capacitor sample/hold circuit.
Typically, the feedback capacitors CFB are precharged to a common mode voltage VCMO at the same time the two input sampling capacitors CIN are being charged to the input voltages Vin+ and Vin−, respectively. It should be appreciated that there are various well-known switched-capacitor DACs which can be used in the above offset-compensated switched capacitor sample/hold circuit 1. The disadvantages are essentially the same for most or all of the variations. For example, more bandwidth is needed for the amplifier, more integrated circuit chip area is required, more parasitic devices are present, and more noise is present because the additional switched capacitors generate increased amounts of kT/C noise which is added to the kT/C noise generated by the input sampling capacitors.
It would be desirable to have a way of implementing the basic functions of the offset-compensated switched-capacitor sample/hold circuits of Prior Art FIGS. 1 and 2 without compromising the speed and noise performance and simplicity of a simple sample/hold circuit. The outputs of the prior art switched-capacitor offset DAC shown in FIGS. 1A and 1B cause substantial capacitive loading on the summing junctions of the operational amplifier 11, thereby degrading the feedback factor and hence the circuit speed and noise. (The feedback factor is the ratio of the feedback capacitance to the sum of the input capacitance and the feedback capacitance, and is proportional to circuit speed and inversely proportional to circuit noise.) The circuit shown in FIG. 2 reduces these problems, but the switched-capacitor offset DACs in both FIGS. 1 and 2 are too large and complex for use with ADCs having multiplexed inputs because their large size and large numbers of capacitors and associated signal routing conductors tends to be incompatible with high-speed, low-noise circuit operation.
Thus, there is an unmet need for faster, lower cost, lower noise offset-compensated switched-capacitor sample/hold circuits and ADCs than have been available in the prior art.